1. Field of the Invention
This invention generally relates to integrated circuit (IC) fabrication and, more particularly, to a system and method for reducing the number of processes involved in etching an indium tin oxide layer (ITO) adjoining a silicon (Si) layer.
2. Description of the Related Art
Liquid crystal displays (LCDs) are now commonly used in handheld devices such as mobile telephones and palm-sized computers. Further, the price and display resolution characteristics of LCDs continue to approach cathode ray tube (CRT) displays. To decrease the size of handheld LCDs and to improve the visual characteristics of desktop LCDs, the geometries of LCD structures must continue to decrease. Therefore, the feature resolution requirements in the formation of LCD structures, such as active matrix (AM) LCD pixels, continue to become more stringent.
ITO (indium tin oxide) is widely used as a material in the fabrication of AM LCD pixel electrodes. ITO dry etching has significant advantages in the controlled etching profiles and features when compared to the conventional ITO wet etching method. This difference is especially telling when the features, such as vias and line widths, are in the range of 3 microns (um), or less. ITO is a material that is difficult to dry etch, however, and study continues into methods to improve the conventional processes. Typically, a very high radio frequency (RF) power or plasma source is needed to perform the ITO dry etch. The problem with using high RF power occurs in the selective etching of the ITO underlayers. One convention ITO underlayer material is silicon. Silicon is common material used between the electrode metal layer and the transistor channel region. The problem is that a halogen ITO dry etching gas, such as Cl2, HCl, HBr and HI, etches silicon at higher etching rate than ITO. Therefore, a process to intentionally etch ITO often unintentionally etches the underlying Si layer.
FIGS. 1-8 depict a conventional process for forming an amorphous silicon (a-Si) AM LCD bottom gate transistor 100 (prior art). The formation of a top gate transistor would be equivalent in most respects. In FIG. 1 a gate material has been deposited over a glass substrate 102 and patterned to form a gate region 104.
In FIG. 2 a gate insulator 200, such as SiNx, is deposited. A layer of a-Si 202 is deposited over the gate insulator 200, and a layer of doped silicon 204, such as n+ Si, is deposited over the a-Si 202.
In FIG. 3 photoresist later 300 is deposited and patterned.
In FIG. 4 a dry etch is preformed to remove portions of the a-Si layer 202 and the n+ Si layer 204. Then, the photoresist 300 (not shown) is etched away.
In FIG. 5 a layer of ITO 500 material is deposited. A layer of source metal 502, such as Al or Ti, is deposited in a pattern over the ITO layer 500. A photoresist layer 504 is deposited over the metal layer 502 and patterned.
In FIG. 6 a dry etch is performed to remove the exposed metal layer 502 and a half ashing is preformed to clean the exposed ITO surface.
In FIG. 7 a wet etch is performed to remove the exposed ITO layer 500. Then, a stripping is performed to remove the remaining photoresist layer 504.
In FIG. 8 another dry etch is performed to remove the exposed n+ Si layer 204. Then, post-etch cleaning process is performed. Subsequent procedures complete the TFT panel fabrication.
It would be advantageous if ITO material could be etched in a dry etch process instead of a wet etch process.
It would be advantageous if the selectivity of ITO material to silicon could be improved.
It would be advantageous if the gases used to dry etch ITO could be made more selective with respect to silicon.
It would be advantageous if a transistor with adjoining layers of metal, ITO, and Si could be etched in a fewer number of process steps.
Accordingly, a method is provided for selectively etching adjoining film layers in the fabrication of a thin film transistor (TFT), such as might be used in an LCD. The method comprises: forming a first silicon layer; forming a second silicon layer overlying the first silicon layer; forming a layer of ITO overlying the second silicon layer; forming a metal layer overlying the ITO layer; forming a patterned photoresist mask overlying the metal layer; dry etching to remove the metal layer, the ITO layer, and the second silicon layer; and, forming an oxide or nitride etch-stop layer overlying the first silicon layer.
Dry etching includes the substeps of: a first dry etching in an atmosphere of mainly HI, HBr, HCl, HI and Ar, Cl2 and He, CF3Cl, CF2Cl2, SiCl4, SiBr4, or combinations of the above-mentioned gases to remove the metal layer, the ITO layer, and the second silicon layer; and, a second dry etch in an atmosphere of more than 10% oxygen, more than 10% nitrogen, or more than a 10% combination of oxygen and nitrogen, to promote the formation of the etch-stop layer in the first silicon layer.
Additional details of the selective ITO/Si etching method are provided below.